Semiconductor devices are continually being developed with an eye toward increased operating speeds at reduced voltages. Also, processes for manufacturing semiconductor devices are being developed with higher degrees of device integration.
For example, in a MOS transistor, a channel length of the MOS transistor may be reduced to increase both operational speed and degree of integration. However, in a planar MOS transistor, as the channel length is reduced, electric fields may affect operation of the planar MOS transistor, for example, due to drain induced barrier lowering (DIBL). Also, a channel-driving capacity of a gate electrode may be deteriorated such that a short channel effects may occur. Furthermore, the mobility of carriers and/or current-driving forces may be reduced due to increased concentration of impurities in the channel region. Moreover, junction leakage current may be increased in accordance with a reduced junction depth of source/drain regions.
To address the above-mentioned problems of two-dimensional planar MOS transistors, three-dimensional transistors have been developed. Examples of the three-dimensional transistor include recessed channel array transistors (RCAT), fin field effect transistors (FinFET), etc. RCATs may have a relatively long channel length and excellent refresh characteristics. However, the RCATs may be limited by a design rule of no more than about 60 nm in view of desired current flow characteristics. In contrast, FinFETs may have excellent current flow characteristics; however, since gate induced drain leakage current (GIDL) may be increased, FinFETs may have poor refresh characteristics.